1. Field of the Invention
The present invention relates to an amplified type solid-state image pickup device, and particularly to a CMOS type solid-state image pickup device using an N/P+ substrate, i.e., so-called CMOS image sensor.
2. Description of the Related Art
Conventionally, as a solid-state image pickup device, a charge coupled device type solid-state image pickup device (hereinafter, CCD image sensor) has been well known. A CCD image sensor is usually formed by using an N-type substrate. Further, a CCD image sensor needs three power supplies whose voltage values are different from one another to be driven. For example, three power supplies of 5 V, 8 V, and 15 V are required for driving a CCD image sensor. In a case of the CCD image sensor, a power consumption thereof is about 500 mW.
Recently, as solid-state image pickup devices, CMOS image sensors using P/P+ substrates have been proposed, and have been commercialized. The CMOS image sensors have a principle of operation (features) different from that of the CCD image sensors. To describe concretely, a CMOS image sensor has features such as a single power supply, low-voltage driving, a low power consumption, and the like. For example, one power supply of 3 V is sufficient for a CMOS image sensor. A power consumption of this CMOS image sensor is about 50 mW.
In recent years, in the same way as a case of CCD image sensors, it has been significantly developed that CMOS image sensors have been made multi-pixel (high-resolution). When the number of pixels (image pickup elements) is increased without change in a size of a sensor, each pixel is naturally miniaturized. Then, an acceptance area of a photo diode in each pixel is reduced in accordance with the miniaturization of the pixels. In accordance therewith, a sensitivity of a photo diode is decreased.
In a case of a CCD image sensor, provided that depletion layers of photo diodes are enlarged, it is possible to increase a sensitivity of the photo diode. However, a CMOS image sensor is structured to be driven at a voltage lower than that of a CCD image sensor. Therefore, as compared with a CCD image sensor, it is difficult to enlarge depletion layers in photo diodes. Namely, in a case of a CMOS image sensor, it is difficult to compensate for a decrease in sensitivity which is caused by miniaturization of pixels by enlarging depletion layers of photo diodes. Accordingly, with respect to a CMOS image sensor, development of a technology in which it is possible to increase a sensitivity by a method different from that for a CCD image sensor, has been an important technical problem for future more high-resolution making (for example, refer to Jpn. Pat. Appln. KOKAI Publication Nos. 2001-160620 and 2001-223351). Further, development of a technology in which not only is it possible to merely increase a sensitivity, but also it is possible to suppress deterioration in image quality such as blooming, color mixture, and the like has been desired.
As one of countermeasures for such a problem, it has been considered to use, for example, an N/P+ substrate. The reason for using an N/P+ substrate is for efficiently collecting electrons generated by photoelectric conversion onto photo diodes. Namely, an N/P+ substrate is structured such that, in the same way as in a case of a P/P+ substrate, an N-type semiconductor layer (N-type epitaxial layer) onto which epitaxial growth has been carried out is laminated on a P+ substrate. Photo diodes (N-type semiconductor layers) are formed by carrying out ion implantation of N-type impurities such as, for example, (P) phosphorus or the like, into the N-type epitaxial layer of the N/P+ substrate with an accelerator. In the photo diodes formed in this way, it is easier to enlarge depletion layers than that in a case of a P/P+ substrate. Therefore, it is possible to increase a sensitivity of photo diodes without increasing a driving voltage of the CMOS image sensor. In accordance therewith, it is possible to utilize a short span of lifetime of carriers, which makes it possible to prevent a deterioration in image quality such as blooming, color mixture, or the like from being brought about. Accordingly, the problem described above can be solved by manufacturing a CMOS image sensor by using an N/P+ substrate.
However, unlike a case in which a CMOS image sensor is manufactured by using a P/P+ substrate, in a case in which a CMOS image sensor is manufactured by using an N/P+ substrate, some characteristic problems caused by an N/P+ substrate are brought about.
First, there is a problem relating to isolation among photo diodes. In a P/P+ substrate, a plurality of photo diodes (N-type semiconductor layers) are formed on a P-type epitaxial layer. Therefore, isolation is certainly carried out among the photo diodes by the P-type semiconductor layer which is a P-type epitaxial layer. Namely, the photo diodes are not connected to one another electrically in any case. In contrast thereto, in an N/P+ substrate, a plurality of photo diodes (N-type semiconductor layers) are formed on an N-type epitaxial layer. Therefore, isolation is not carried out among the photo diodes, and a problem that the photo diodes are connected to one another electrically is brought about.
Secondly, there is a problem relating to a leak current. In a case of a P/P+ substrate, the P-type semiconductor layer appears on a cut surface of each chip by a dicing process in which each of a plurality of semiconductor chips is divided from one sheet of Si (silicon) wafer. In contrast thereto, in a case of an N/P+ substrate, a PN junction surface which is an interface between a P+ type substrate main body and an N-type epitaxial layer appears on a cut surface of each chip. When a PN junction surface appears on a cut surface of a chip, the cut surface causes generation of a leak current, or could be a flow path of a leak current. Namely, there is increased a concern that an increase in a leak current is caused.
Thirdly, there is a problem relating to circuits disposed at a periphery of an image pickup area. As one of the features of a CMOS image sensor, there is an example in which various signal processing circuits (peripheral circuits) can be made to be an on-chip circuit along with image pickup elements. Namely, unlike CCD image sensors, because a manufacturing process for CMOS image sensors is similar to that for logic circuits, those can be manufactured on the same manufacturing line. Further, as described above, because a CMOS image sensor can be driven by a single power supply and at a low voltage, a power supply for logic circuits can be used as a driving power supply thereof. In this way, when a P/P+ substrate is used in a CMOS image sensor which can be made to be one chip, a P-well at which the peripheral circuits are formed can be grounded via the P+ type substrate main body. In accordance therewith, it is possible to make pulse signals generated in the peripheral circuits, in particular, logic circuits and an analog circuit favorable so as to have stable waveforms. Namely, when a P/P+ substrate is used, it is possible to make a CMOS image sensor be a multi-pixel or high-speed type.
In contrast thereto, when an N/P+ substrate is used, a P-well at which peripheral circuits are formed and a P+ substrate main body are isolated by an N-type epitaxial layer. Therefore, the P-well cannot be grounded via the P+ substrate main body. Namely, because a ground potential (Vss) can be taken only from the P-well, a zero potential of the P-well which cannot be grounded is unstable. Therefore, rising edges/down edges of pulses are delayed in the peripheral circuits, in particular, an analog circuit in some cases, which causes a problem that only nonrectangular pulses with unstable waveforms can be generated, or timings in generating pulses are shifted. These problems cause that a defect in image property such as vertical stripes and horizontal stripes, and the like appears in an image pickup device with the number of pixels of 2M bits or more and a high-speed image pickup device in which the number of frames in image-pickup per second is 30 frames or more.